1. Field of the Invention
This invention relates generally to testing of integrated circuits using parallel scan paths and particularly relates to testing those integrated circuits using serial to parallel and parallel to serial registers to move test information to and from the integrated circuit.
2. Description of the Related Art
Cost effective testing of today's complex integrated circuits is extremely important to semiconductor manufacturers from a profit and loss standpoint. The increases in complexity of state-of-the-art integrated circuits is being accompanied by an ever increasing difficulty to test the integrated circuits. New test techniques must be developed to offset this increasing integrated circuit test cost, otherwise further advancements in future integrated circuit technology may be blocked. One emerging technology that is going to accelerate the complexity of integrated circuits even more is intellectual property cores. These cores will provide highly complex pre-designed circuit functions such as; DSPs, CPUs, I/O peripherals, memories, and mixed signal A/D and D/A functions. These cores will exist in a library and can be selected and placed in an integrated circuit to quickly provide a complex circuit function. The low cost testing of integrated circuits that contain highly complex core functions will be a significant challenge